数字电子技术试验报告

数字电子技术试验报告

武汉职业技术学院电信学院

数字电子技术实验报告

实验科目:数字电子技术实验（五）

实验名称:译码显示电路的应用

实验专业:光电子技术光电09305

实验者：朱军

实验时间:201*年11月8日

实验指导教师:黄老师

武汉职业技术学院

实验（训）项目单(Trainingitem)编制部门：电子资讯工程学院编制人：朱军日期：201*.11.08

项目编号课程名称训练目的五项目名称译码显示电路的应用教材训练对象电信工程学院电子类学生学时3数字电子技术实验数字电子技术、电子技能实训1)掌握中规模集成电路的功能。2)学习共阴极七段显示器的使用方法。3)学会中规模集成数字电路的分析方法、设计方法和测试方法。1．实训设备和器件数字电路实验箱、共阴极七段显示器、74LS48芯片一片、74LS04芯片两片、导线若干74LS4874LS04数字电路实验箱七段数码显示器七段数码显示器74LS4874SL042．实训电路图

3．内容及实训步骤：（1）测74LS48的功能测74LS48的功能，直接将七个共阴极的发光二极管与74LS48的输出端连接，然后再一一检测。①器件检测。用万用表欧姆档测量连接导线的好坏，然后将这些导线将发光二极管与电源+5V连接，检测发光二极管的好坏。②74LS48检测。a.将集成块输出端与发光二极管连接起来，同时用铅笔做上记号，标注a-g的字母。然后再将输入端与开关（共地）连接起来，Vcc、GND分别接电源+5V和地。b.让试灯输入端，灭灯输入端分别接低电平和高电平，如果所有的发光二极管都亮，说明集成块是好的。c.再测试集成块其它的功能，功能表如下：功能或数字灭灯试灯动态灭零0123456789输入LT×011111111111RBI××01×××××××××A3××00000000001A2××00001111000A1××00010011001A0××00100001000BI/RBI0（输入）101111111111输出a0101011011110b0101111101110c0101101111110d0101011010111e0101010000101f0101000110110g0100011110111显示字形灭灯灭灯（2）组成一个将二进制（BCD码）译成以十进制数方式显示的电路由于74LS48正常工作时输出的是高电平，而本数字实验箱上的七段显示器是共阳极的，所以要将输出电平反向后才输入到显示器中。74LS04中含有六个反向器，因此此试验要用两片。a.在应用74LS04之前，还是需要逐个的对每个反向器进行检测，以判断所有的反向器是不是都是好的。方法是在一个反向器输入端接开关，输出端接发光二极管，同时Vcc和GND分别接+5V和地，然后将开关波动，输入高电平时，二极管不亮；输入低电平时，二极管亮。b.在检测74LS48的功能的基础上，按照电路图将74LS48和74LS04、七段共阳极显示器连接起来。然后改变各输入端的状态，观察显示器的变化，记录的结果如上。4．实训总结与分析⑴由实验可知，若当BI/RBO做输入端时,且BI=0时，无论输入状体如何，显示都为零。⑵当试灯输入LT=0时，，BI/RBO是输出端，且RBO=1，此时所有显示段都发亮，显示字形“8”。所以该输入端可用于检查74LS48本身及显示器的好坏。⑶当RBI=0、LT=1、输入代码A3A2A1A0=0000时，数码段无任何显示。

扩展阅读：数字电子技术实验报告

数字电子技术实验报告

院系：电气工程学院专业：电气工程及自动化年级：201*班号：0802姓名：学号：

0

","p":{"h":14.971,"w":3.05,"x":135.187,"y":1174.078,"z":1},"ps":{"_enter":1},"t":"word","r":[11]}],"page":{"ph":1263.375,"pw":893.25,"iw":0,"ih":0,"v":6,"t":"4","pptlike":false,"cx":135.187,"cy":114.937,"cw":629.354,"ch":1074.112}})目录

实验一组合逻辑电路分析....................................................................2

一、实验目的..........................................................................2二、预习内容..........................................................................2三、实验元件..........................................................................2四、实验内容..........................................................................3五、实验数据及结果....................................................................4六、实验总结..........................................................................4实验二组合逻辑实验（一）................................................................5半加器和全加器.............................................................................5

一、实验目的..........................................................................5二、预习内容..........................................................................5三、实验元件..........................................................................5四、实验内容..........................................................................7五、实验数据及结果....................................................................8六、实验总结..........................................................................9实验三组合逻辑实验（二）................................................................10数据选择器和译码器的使用..................................................................10

一、实验目的.........................................................................10二、预习内容.........................................................................10三、实验元件.........................................................................10四、实验内容.........................................................................12五、实验数据及结果...................................................................14六、实验总结.........................................................................15实验四触发器和计数器.....................................................................16

一、实验目的.........................................................................16二、预习内容.........................................................................16三、实验元件.........................................................................16三、实验内容及结果...................................................................19四、实验总结.........................................................................22实验五555集成定时器.....................................................................23

一、实验目的.........................................................................23二、预习内容.........................................................................23三、实验元件.........................................................................23四、实验内容及效果","p":{"h":13.5,"w":6.75,"x":288.375,"y":911.728,"z":174},"ps":null,"t":"word","r":[6]},{"c":"...................................................................28五、实验总结.........................................................................31实验六数字秒表...........................................................................32

一、实验目的.........................................................................32二、预习内容.........................................................................32三、实验元件.........................................................................32四、设计内容及要求...................................................................32五、原理框架图.......................................................................32六、实验电路图以及简单分析...........................................................33七、实验体会.........................................................................33

1

实验一组合逻辑电路分析

一、实验目的

1、了解熟悉各个逻辑元件的使用。2、熟悉了解组合逻辑电路的分析。

二、预习内容

1、复习组合逻辑电路的分析的原理和方法。2、复习各种逻辑元件的使用。

三、实验元件

1、四2输入与非门74LS00

其结构及引脚如图所示：

","p":{"h":18.458,"w":6.772,"x":710.775,"y":593.062,"z":51},"ps":null,"t":"word","r":[13]},{"c":"。其中14号引脚接+5V高电平，7号引脚接地。其逻辑关系表达式为Y=AB

2、双4输入与非门74LS20

其结构及引脚如图所示：

其中14号引脚接+5V高电平，7号引脚接地。其逻辑关系表达式为Y=ABCD

2

1、分析下图组合逻辑电路并将数据记录下来。

VCC5VJ1X11U1A5Key=174LS00DJ22VCC02.5VU1C7Key=274LS00DJ33U1B6Key=3J4474LS00DKey=4

2、密码锁

密码锁的开锁条件是：拨对密码，钥匙插入锁眼将电源接通，当两个条件同时满足时，开锁信号为“1”，将锁打开。否则，报警信号为“1”，接通警报，分析密码ABCD是什么。

VCC5VVCC5VJ131112","p":{"h":5.894,"w":6.8,"x":723.237,"y":832.329,"z":579},"ps":{"_cover":true,"_enter":1,"_scaleX":0.998},"t":"word","r":[27]},{"c":"密码锁电路图为：

X12.5VX22.5VKey=1J21VCC0VCCU2B74LS00DU1A4U2C74LS00D10U3A7U1C8U1DKey=2974LS00D52J3U1B74LS20D74LS00D74LS00DU2A74LS00D74LS00D6Key=3J4Key=4

3

1、组合逻辑电路真值表

A0000000011111111B0000111100001111C0011001100110011D0101010101010101Y0001000100011111=AB+CD由真值表得出逻辑关系表达式为Y=ABCD

2、密码锁的真值表如下

A0000000011111111B0000111100001111C0011001100110011D0101010101010101X1000","p":{"h":16.966,"w":7.774,"x":602.79,"y":685.128,"z":441},"ps":{"_cover":true,"_scaleX":0.916},"t":"word","r":[10]},{"c":"0000001000000X21111111110111111即由真值表可得密码锁的密码为ABCD=1001

六、实验总结

1、通过实验重新了解认识了组合逻辑电路分析的步骤，由逻辑电路推导出组合逻辑电路的真值表和逻辑表达式的方法

2、通过这次实验更加了解了了元件74LSS00和74LS20的内部结构和引脚的使用。

4

组合逻辑实验（一）

半加器和全加器

一、实验目的

熟悉用门电路设计组合电路的原理和方法步骤

二、预习内容

1、复习用门电路设计组合逻辑电路的原理和方法2、复习二进制数的运算

3、利用下列元器件完成：

（1）完成“异或”门、“与非”门、“与或非”门设计全加器的逻辑图。

（2）完成用“异或”门设计的3变量判奇电路的原理图。

三、实验元件

1、四位全加器74LS283

其逻辑及引脚图如图所示：

其中16接+5V高电平，8端口接地，端口12、14、3、5对应的加数的A3A2A1A0","p":{"h":13.184,"w":6.232,"x":744.569,"y":1072.537,"z":83},"ps":null,"t":"word","r":[16]},{"c":"，端口11、15、2、6对应的被加数B3B2B1B0，端口10、13、1、4对应的相加的和S3S2S1S0，端口7对应的为相加前的进位C1，端口9对应的相加后的进位C3。

5

、","p":{"h":17.466,"w":4.378,"x":158.804,"y":111.465,"z":4},"ps":null,"t":"word","r":[5]},{"c":"与或非门74LS51

其逻辑及引脚图如图所示：

端口14接+5V高电平，端口7接高电平，其他端口对应数据符号如图所示，逻辑表达式如上图。

3、异或门（OC门）74LS136

其逻辑及引脚图如图所示：

端口14接+5V高电平，端口7接地，其他端口输入如图所示，其逻辑表达式为Y=AB。

6

1、用与非门组成半加器

设计电路图如图所示：

VCC5VVCCX12.5VU1DJ1146X22.5V74LS00DU1AU2AKey=10U1C574LS00DJ274LS00D274LS00DKey=2U1B7374LS00D

如图连接电路按照表格中的数据设置电路数据，测量结果记录入表格中。

2、用异或门、与或非门、与非门组成全加器

设计电路图如图所示：

VCC5VJ1VCC5VVCCVCCVCC5VX1X22.5V2.5VKey=101","p":{"h":8.027,"w":4.558,"x":301.371,"y":779.732,"z":515},"ps":{"_cover":true,"_enter":1,"_scaleX":1.001},"t":"word","r":[33]},{"c":"R11.0kU1AU1B4R21.0kJ2274LS136DVCC74LS136D3Key=2J3571121391011U2A86U3AKey=374LS00D74LS51D

如图连接电路按照表格中的数据设置电路数据，测量结果记录入表格中。

7

、用异或门设计3变量判奇电路，要求变量中的1的个数为奇数时，输出为1。否则输出

为0。

设计电路如图所示：

VCC5VJ1VCC5VVCCVCCVCC5VX1Key=101R11.0kU1AU1B4R21.0k2.5VJ23274LS136DVCC74LS136DKey=2J35Key=3

如图连接电路按照表格中的数据设置电路，测量结果记录入表格中。4、“74LS283”全加器逻辑功能能测试。","p":{"h":17.466,"w":3.559,"x":135.187,"y":720.6,"z":37},"ps":null,"t":"word","r":[1]},{"c":"

连接元件74LS283，如表格中所示设置全加器数据并测试结果记录入表格。

五、实验数据及结果

1、用与非门组成半加器

iBi+AiBi；Ci=AiBi逻辑表达式为：Si=A

与理论相符合。

8

、用异或门、与或非门、与非门组成全加器数据表格。

逻辑表达式为：Si=AiBiCi1；Ci=AiBi+(AiBi)Ci1与理论相符合。

3、用异或门设计3变量判奇电路。

输入A输入B输入C输出L

00000011010101101001101011","p":{"h":17.507,"w":7.829,"x":668.292,"y":460,"z":148},"ps":{"_cover":true,"_scaleX":0.894},"t":"word","r":[18]},{"c":"001111实验数据与理论值相同。

4、“74LS283”全加器逻辑功能测试

测试结果与理论值相同。

六、实验总结

1、通过自己设计运行全加器和设计3变量判奇电路更加了解全加器的内部结构和异或

门与或非门与或门的使用。

2、通过74LS283逻辑功能的验证更加熟悉了解了全加器的使用。

9

组合逻辑实验（二）数据选择器和译码器的使用

一、实验目的

熟悉数据选择器和数据分配器的逻辑功能和掌握其使用方法。

二、预习内容

1、了解所用元件的逻辑功能和管脚排列。2、复习有关数据选择器和译码器的内容。

+3、用八选一数据选择器产生逻辑函数L=ABC+ABCABC","p":{"h":18.459,"w":8.867,"x":661.2,"y":487.237,"z":59},"ps":null,"t":"word","r":[13]},{"c":"+ABC和

L=ABC。

4、用3线-8线译码器和与非门构成一个全加器。

三、实验元件

1、数据选择器74LS151

其管脚端口如图所示：

10

当使能端EN=0是，Y是A2、A1、A0和输入数据D0~D7的与或函数，其表达式为：Y=7i=0miDi，式中mi是A2、A1、A0构成的最小项，显然当Di=1时，其对应的最小项mi在于或表达式中出现。当Di=0时，对应的最小项就不出现。

2、3-8线译码器74LS138其管脚端口如图所示：

74HC138管脚图:74LS138为3线－8线译码器，共有54/74S138和54/74LS138两

种线路结构型式，其工作原理如下：

当一个选通端（G1）为高电平，另两个选通端（/(G2A)和/(G2B)）为低电平时，可将地址端（A、B、C）的二进制编码在一个对应的输出端以低电平译出。

利用","p":{"h":15.75,"w":31.537,"x":193.77,"y":1000.995,"z":107},"ps":null,"t":"word","r":[2]},{"c":"G1、/(G2A)和/(G2B)可级联扩展成24线译码器；若外接一个反相器还可级联扩展成32线译码器。

若将选通端中的一个作为数据输入端时，74LS138还可作数据分配器。3线-8线译码器74LS138的功能表如下图：

11

四、实验内容

1、数据选择器的使用

将数据选择器的地址信号A2、A1、A0作为函数的输入变量，数据输入D0~D7作为控制信

号，控制各最小项在输出逻辑函数中是否出现，使能端EN始终保持低电平，这样，八选一数据选择器就成为一个三变量的函数产生器。

（1）用八选一数据选择器74LS151产生逻辑函数

将表达式写为：L=m1D1+m3D3+m6D6+m7D7

该式符合标准表达式，显然令D1、D3、D5、D7都应该等于1，而式中没有出现的最小项m0、m2、m4、m5，他们的控制信号D0、D2、D4、D5都应该等于0。由此可画出该逻辑函数产生器的逻辑图。

L=A","p":{"h":18.458,"w":9.812,"x":331.155,"y":924.112,"z":111},"ps":null,"t":"word","r":[9]},{"c":"BC+ABC+ABC+ABC

12

5VVCC5VX12.5VU1J143D0542D1Y1D26Key=1VCCGND15D3~W14D413D5GND12D6D7J2121110A9BC7~GKey=2374LS151DVCCJ3GNDKey=3GND2）用八选一数据选择器74LS151产生逻辑函数

根据上述74LS151的工作原理自行设计逻辑图完成逻辑函数L=ABC

VCCVCCX15V5V2.5VVCCU1J143D0Y542D11D215D3~W6Key=1GND14D413D512D6GNDD7J2","p":{"h":13.835,"w":13.085,"x":295.124,"y":889.836,"z":350},"ps":{"_cover":true,"_enter":1,"_scaleX":0.998},"t":"word","r":[36]},{"c":"121110A9BC7~GKey=2374LS151DVCCJ3GNDKey=3GND13

（

、3-8线译码器的应用

用3-8线译码器74LS138和与非门构成一个全加器。写出逻辑表达式并设计电路图验证试验结果。

VCC5VVCC5V2.5V2.5VX1X2J1VCC11U114U2A12Key=1GND2123645ABCG1~G2A~G2BJ23Y0Y1Y2Y3Y4Y5Y6Y715141312111097569871074LS20DU2BKey=2VCCGND74LS138D74LS20DJ3GNDKey=3GND

五、实验数据及结果

1、数据选择器的使用

（1）用八选一数据选择器74LS151产生逻辑函数L=ABC+ABC+ABC+ABC真值表如下图：

输入A输入B输入C输出L

00000011010001111000101011011111即可得函数表达式为：L=","p":{"h":15.75,"w":11.765,"x":305.25,"y":1088.82,"z":228},"ps":null,"t":"word","r":[28]},{"c":"ABC+ABC+ABC+ABC

14

2）用八选一数据选择器74LS151产生逻辑函数L=ABC

真值表如下图

输入A输入B输入C输出L

00000011010101101001101011001111即可得函数表达式为：L=ABC

2、3-8线译码器的应用

真值表如图所示：

输入A输入B输入C输出L1输出L201*0000110010100110110010101011100111111即可得其逻辑表达式为：L1=ABC；L2=AB+(AB)C符合全加器逻辑关系，完成实验。

六、实验总结","p":{"h":23.662,"w":5.205,"x":280.47,"y":794.878,"z":348},"ps":{"_enter":1},"s":{"font-family":"e4e587976bec0975f465e2af0080010"},"t":"word","r":[19]},{"c":"1、通过该实验对于数据选择器74LS151和数据译码器74LS138的功能有了更清楚的认识了解。

2、通过自己根据逻辑关系设计电路熟悉和掌握电路的设计。

15

触发器和计数器

一、实验目的

1、熟悉J-K触发器的基本逻辑功能和原理。2、了解二进制计数器的工作原理。

3、设计并验证十进制、六进制计数器。

二、预习内容

1、复习有关R-S触发器、J-K触发器、D触发器的内容。

2、预习有关计数器的工作原理。

3、用74LS163和与非门组成四位二进制计数器，十进制计数器，六十进制计数器。设计电路图。

三、实验元件

1、四2输入与非门74LS00其结构及引脚如图所示：

。其中14号引脚接+5V高电平，7号引脚接地。其逻辑关系表达式为Y=AB

此实验中将管脚12与13或者10","p":{"h":17.466,"w":16.984,"x":375.12,"y":1024.65,"z":82},"ps":null,"s":{"letter-spacing":"1.013"},"t":"word","r":[8]},{"c":"与9或者1与2或者4与5连接起来将与非门当做反

相器来使用。

16

、可预置四位二进制计数器74LS163（同步清零）

74LS163的管脚图如下图所示：

74LS163的真值表如下图所示：

PTCP功能1111↑计数φφ01↑并行输入0111φ保持1011φ保持(RC=0)0φφ","p":{"h":16.189,"w":8.438,"x":372.87,"y":707.599,"z":395},"ps":{"_cover":true},"t":"word","r":[17]},{"c":"0φ清零74LS163逻辑功能表74LS163的时序图如下图所示：

17

、七段译码驱动器74LS248

七段译码驱动器74LS248管脚图如下图所示：","p":{"h":15.75,"w":3.559,"x":480.975,"y":135.12,"z":8},"ps":{"_enter":1},"t":"word","r":[1]},{"c":"

七段译码驱动器74LS248功能表如下图所示：

18

1、六进制计数器

根据74LS163以及74LS00的逻辑功能设计出电路图如下图所示。

U2DCD_HEXVCC5V3456710VCC14321U1GNDABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211155432912U3A74LS00D6V120Hz5VGND74LS163DGND试验成功。","p":{"h":17.466,"w":3.559,"x":135.187,"y":927.795,"z":24},"ps":null,"t":"word","r":[4]},{"c":"

GND

电脑仿真以及实验接线如上图，观察数字等显示为0~5的范围，及满足六进制计数器规则，

19

、十进制计数器

根据74LS163以及74LS00的逻辑功能设计出电路图如下图所示。

U2DCD_HEXVCC5V3456710VCC14321U1GNDABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211155432912U3A74LS00D6V120Hz5VGND74LS163DGND

GND

电脑仿真以及实验接线如上图，观察显示数字范围为0~9，即满足十进制显示规则，实验成","p":{"h":15.75,"w":234.391,"x":524.925,"y":766.8,"z":19},"ps":null,"s":{"letter-spacing":"-0.132"},"t":"word","r":[5]},{"c":"功。

20

、六十进制计数器

根据74LS163、74LS248以及74LS00的逻辑功能设计出电路图如下图所示。

U2U5VCC5V3456710911DCD_HEXU1ABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211154657DCD_HEX432143212U3A74LS00D32V120Hz5VGND74LS163DGND11GNDVCCU43456710912ABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO14131211158974LS163D10","p":{"h":8.485,"w":9.763,"x":352.896,"y":720.265,"z":464},"ps":{"_cover":true,"_enter":1,"_scaleX":0.998},"t":"word","r":[23]},{"c":"U6A74LS00DGND

电脑仿真如上图，数字显示范围为0~59，满足六十进制规则，试验成功。

21

GNDVCC5VVCC5V3456710911GNDCKGNDU4CKU5ABCDEFGABCDEFGU1ABCDENPENT~LOAD~CLRCLKQAQBQCQDRCO141312111510467VCCU67126354ABCD~LT~RBI~BI/RBOOAOBOCODOEOFOG131211109151419202122232425VCCU3A74LS00D274LS248DV11Hz5V74LS163D121314151617182U2GNDU7QAQBQCQDRCO141312111538953456710912ABCDENPENT~LOAD~CLRCLK7126354ABCD~LT~RBI~BI/RBOOAOBOCODOEOFOG1312111091514U3B74LS00D74LS248D74LS163D11GND

操作实验接线如上图，观察数字显示范围为0~59，满足六十进制规则，试验成功。

四、实验总结

1、通过该实验更加熟悉了解了可预置四位二进制计数器74LS163的功能和使用。

2、通过该实验熟悉掌握了用可预置四位二进制计数器74LS163","p":{"h":17.466,"w":52.983,"x":504.629,"y":829.845,"z":20},"ps":null,"t":"word","r":[30]},{"c":"设计完成各种进制的计数器。

22

555集成定时器

一、实验目的

熟悉与使用555集成定时器

二、预习内容

复习有关555集成定时器的内容和常用电路。

三、实验元件

555集成定时器：

555时基电路是一种将模拟功能与逻辑功能巧妙地结合在同一硅片上的组合集成电路。该电路可以在最基本的典型应用方式的基础上，根据实际需要，经过参数配置和电路的重新组合，与外接少量的阻容元件就能构成不同的电路，因而555电路在波形的产生与变换、测量与控制、家用电器、电子玩具等许多领域中都得到了广泛应用。","p":{"h":15.75,"w":3.559,"x":592.5,"y":627.15,"z":41},"ps":null,"t":"word","r":[9]},{"c":"

（一）555集成定时器的内部结构和逻辑功能

1.内部结构及逻辑功能

23

图1为555时基电路的电路结构和8脚双列直插式的引脚图，由图可知555电路由电阻分压器、电压比较器、基本RS触发器、放电管和输出缓冲器5个部分组成。它的各个引脚功能如下：

1脚：GND(或Vss)外接电源负端VSS或接地，一般情况下接地。

8脚：VCC(或VDD)外接电源VCC，双极型时基电路VCC的范围是4.5～16V，CMOS型时基电路VCC的范围为3～18V。一般用5V。

3脚：OUT（或Vo）输出端。2脚：TR低触发端。6脚：TH高触发端。

4脚：R是直接清零端。当R端接低电平，则时基电路不工作，此时不论TR、TH处于何电平，时基电路输出为“0”，该端不用时应接高电平。

5脚：CO(或VC)为控制电压端。若此端外接电压，则可改变内部两个比较器的基准电压，当该端不用时，应将该端串入一只0.01μF电容接地，以防引入干扰。

7脚：D放电端。该端与放电管集电极相连，用做定时器时电容的放电。电阻分压器由三个5kΩ的等值电阻串联而成。电阻分压器为比较器C1、C2提供参考电压，比较器C1的参考电压为2/3Vcc，加在同相输入端，比较器C2的参考电压为1/3Vcc，加在反相输入端。比较器由两个结构相同的集成运放C1、C2组成。高电平触发信号加在C1的反相输入端，与同相输入端的参考电压比较后，其结果作为基本RS触发器R端的输入信号；低电平触发信号加在C2的同相输入端，与反相输入端的参考电压比较后，其结果作为基本RS触发器S端的输入信号。基本RS触发器的输出状态受比较器C1、C2的输出端控制。

在1脚接地，5脚未外接电压，两个比较器C1、C2基准电压分别为2/3Vcc，1/3Vcc的情况下，555时基电路的功能表如表1示。","p":{"h":15.75,"w":3.559,"x":431.4,"y":837.72,"z":162},"ps":{"_enter":1},"t":"word","r":[1]},{"c":{"ix":0,"iy":0,"iw":893,"ih":230},"p":{"h":230,"opacity":1,"w":893.249,"x":0,"y":110,"z":163},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_25_163.png"},"t":"pic"},{"c":{"ix":0,"iy":235,"iw":893,"ih":274},"p":{"h":274,"opacity":1,"w":893.249,"x":0,"y":860.25,"z":164},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_25_164.png"},"t":"pic"},{"c":"

24

时基电路的主要参数

555时基电路的主要参数有电源电压、静态电流、定时精度、阈值电压、阈值电流、触发电压、触发电流、复位电压、复位电流、放电电流、驱动电流及最高工作频率。

（二）555集成定时器的应用1．单稳态电路

前面介绍的双稳态触发器具有两个稳态的输出状态

和

，两个状态始终相反。而单

稳态触发器只有一个稳态状态。在未加触发信号之前，触发器处于稳定状态，经触发后，触发器由稳定状态翻转为暂稳状态，暂稳状态保持一段时间后，又会自动翻转回原来的稳定状态。单稳态触发器一般用于延时和脉冲整形电路。

单稳态触发器电路的构成形式很多。图下图所示为用555定时器构成的单稳态触发器，R、C为外接元件，触发脉冲u1由2端输入。5端不用时一般通过0.01uF电容接地，以防干扰。下面对照图进行分析。","p":{"h":15.75,"w":189.412,"x":135.187,"y":978.495,"z":57},"ps":null,"t":"word","r":[4]},{"c":{"ix":0,"iy":0,"iw":893,"ih":478},"p":{"h":478,"opacity":1,"w":893.25,"x":0,"y":231,"z":58},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_26_58.png"},"t":"pic"},{"c":{"ix":0,"iy":483,"iw":893,"ih":22},"p":{"h":22,"opacity":1,"w":893.249,"x":0,"y":821,"z":59},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_26_59.png"},"t":"pic"},{"c":{"ix":0,"iy":510,"iw":893,"ih":25},"p":{"h":25,"opacity":1,"w":893.249,"x":0,"y":818,"z":60},"ps":null,"s":{"pic_file":"/home/iknow/conv//data//bdef//36677606//36677606_26_60.png"},"t":"pic"},{"c":"

25

(1)稳态

接通电源后，

经R给电容C充电，当uc上升到大于

时，基本RS触发器复位，，若不加触发信号，即

输出u0=0。同时，晶体管T导通，使电容C放电。此后uc，则u0保持0状态。电路将一直处于这一稳定状态。

(2)暂稳态

在t=t1瞬间，2端输入一个负脉冲，即u1触发器保持原状态，u0仍为高电平。在t=t3时刻，当uc上升略高于

时，

=0，

=1，基本RS触发器复位，输出

)，若ucord","r":[0]}],"page":{"ph":1263.375,"pw":893.25,"iw":893,"ih":997,"v":6,"t":"4","pptlike":false,"cx":0,"cy":108,"cw":893.25,"ch":1081.049}})2．多谐振荡器

多谐振荡器又称为无稳态触发器，它没有稳定的输出状态，只有两个暂稳态。在电路处于某一暂稳态后，经过一段时间可以自行触发翻转到另一暂稳态。两个暂稳态自行相互转换而输出一系列矩形波。多谐振荡器可用作方波发生器。

如下图所示是由555定时器构成的多谐振荡器。R1、R2和C是外接元件。

刚接通电源时，uc=0，u0=1。当uc升至

后，比较器C1输出低电平(

=0)，基本

RS触发器置0，定时器输出u0由1变为0。同时，三极管T导通，电容通过R2放电，uc下降。在输出低电平(

"style","c":[0],"s":{"bold":"true","font-size":"23.662"}},{"t":"style","c":[0,2,3,4,5,6,7,8,9,15,16,17,22,23,24,1],"s":{"color":"#000000"}},{"t":"style","c":[6,8,2],"s":{"font-family":"e4e587976bec0975f465e2af005001d"}},{"t":"style","c":[4,6,7,8,23,3],"s":{"font-size":"15.75"}},{"t":"style","c":[7,4],"s":{"font-family":"e4e587976bec0975f465e2af001001d"}},{"t":"style","c":[4,7,24,5],"s":{"font-family":"e4e587976bec0975f465e2af001001d"}},{"t":"style","c":[8,6],"s":{"font-size":"15.75"}},{"t":"style","c":[7],"s":{"letter-spacing":"-0.11"}},{"t":"style","c":[8],"s":{"letter-spacing":"0.037"}},{"t":"style","c":[9],"s":{"color":"#000000"}},{"t":"style","c":[9,11,14,18,20,21,10],"s":{"font-family":"e4e587976bec0975f465e2af00b001d","font-size":"12.409"}},{"t":"style","c":[21,11],"s":{"letter-spacing":"-0.16"}},{"t":"style","c":[13,17,12],"s":{"font-family":"e4e587976bec0975f465e2af00c001d"}},{"t":"style","c":[13],"s":{"color":"#ff0000","font-size":"9.012"}},{"t":"style","c":[20,14],"s":{"letter-spacing":"-1.096"}},{"t":"style","c":[16,17,15],"s":{"font-size":"10.135"}},{"t":"style","c":[16],"s":{"font-family":"e4e587976bec0975f465e2af013001d","letter-spacing":"-0.465"}},{"t":"style","c":[17],"s":{"font-family":"e4e587976bec0975f465e2af00c001d","letter-spacing":"-0.495"}},{"t":"style","c":[20,21,18],"s":{"color":"#0000ff"}},{"t":"style","c":[18,20,21,19],"s":{"color":"#0000ff"}},{"t":"style","c":[20],"s":{"color":"#0000ff"}},{"t":"style","c":[21],"s":{"color":"#0000ff"}},{"t":"style","c":[23,22],"s":{"font-family":"e4e587976bec0975f465e2af009001d"}},{"t":"style","c":[23],"s":{"font-family":"e4e587976bec0975f465e2af009001d"}},{"t":"style","c":[24],"s":{"font-size":"13.5"}}],"body":[{"c":"四、实验内容及效果

1、555单稳电路根据555集成定时器的内部结构和原理设计555单稳电路如下图所示：

R2=100KΩ时，

VCC5VVCCX1U1555_TIMER_RATEDVCCRSTDISTHROUT42.5VR1100k213TRICONGNDV11kHz5VC110uF-POL0C210nF理论上tw=RCln3=1.1RC≈1.1s

仿真实验时，在运行时间t=1.1时，等熄灭一下。运用示波器观察当时时刻波形显示如图所示：

实际操作实验时，指示灯也在约为1秒左右时熄灭一瞬间，即实验与理论值基本相同，试验成功。

28

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VCC5VU1555_TIMER_RATEDR11.0MRST1VCCX12.5VVCCOUT4DISTHR23TRICONGNDV11kHz5VC110uF-POL0C210nF

理论上tw=RCln3=1.1RC≈11s

仿真实验时，在运行时间t=11时，等熄灭一下。运用示波器观察当时时刻波形显示如图所示：

实际操作实验时，指示灯也在约为11秒左右时熄灭一瞬间，即实验与理论值基本相同，试验成功。

29

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根据555集成定时器的内部结构和原理设计555多谐振荡器电路如下图所示：

VCC5VVCCGXSC1U1555_TIMER_RATEDABCDTR1100k1VCCRSTOUT4R210k23DISTHRTRICONGNDC1270pFC210nF0示波器仿真结果如下图：

根据连读元件参数计算理论值为：

f=

tpL

11.43

=+tpHR1+2R2C其中tpL=0.7R2C，tpH=0.7（R1+R2）C，根据示波器显示以及比例符合理论值，试验成功。

30

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根据555集成定时器的内部结构和原理设计接近开关电路如下图所示：接近开关要求触摸一下接触线，LED亮一秒钟。

VCC5VU1555_TIMER_RATEDVCCR1100kRSTDIS1VCCOUT2THRTRI3C3100nFCONGNDC14.7uF-POLC210nF0LED1

从2号端口接出一根导线，将另一端口放向远处，当有任何物体接近导线端口或者移动改变导线端口灯亮，及与理论效果相同，试验成功。

五、实验总结

1、通过该实验不仅让我们从理论上更从实践上熟悉了解了555集成定时器的内部结构以及

逻辑功能。2、通过这次实验熟悉掌握了555集成定时器的各种用法以及功能。

31

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一、实验目的

1、了解数字计时装置的及泵年工作原理和简单设计方法。

2、熟悉中规模集成器件和半导体显示器的使用。

3、了解简单数字装置的调试方法，验证所涉及的数字秒表的功能。

二、预习内容

1、N进制计数器、译码显示电路以及多谢振荡器的工作原理和设计方法。2、所用期间的功能和外部引线排列。

三、实验元件

555集成定时器、四2输入与非门74LS00、可预置四位二进制计数器74LS163、双4输入与非门74LS20、七段译码驱动器74LS248以及相关元件。

四、设计内容及要求

1、设计一个数字秒表电路，电路包含秒脉冲发生器、计数、译码。显示范围为：00~592、数字秒表电路应具有清零、停止、启动的功能。

五、原理框架图

译码电路译码电路数码显示器译码电路秒计数器32

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GNDGNDGNDVCC5VGNDCKGNDCKU4J1Key=2J2Key=1U13451659U5ABCDEFGABCDEFGU6QAQBQCQDRCO14131211154849VCCGNDR1100k63U9555_TIMER_RATEDVCCRSTDIS6462ABCDENPENT~LOAD~CLRCLK7126354ABCD~LT~RBI~BI/RBO710912OAOBOCODOEOFOG131211109151440414243444546U3COUT60U3A74LS00D74LS248DR2100k74LS00DTHRTRICONGND74LS163D53475033343536373839C2C14.7uF10nFU3B74LS00D61U257U7QAQBQCQDRCO1413121115515554523456710912ABCDENPENT~LOAD~CLRCLK7126354ABCD~LT~RBI~BI/RBOOAOBOCODOEOFOG1312111091514U8A74LS20D5674LS248D74LS163D

电路中555集成定时器以及相关电阻电容构成的为秒信号发生器，其频率根据实验五中555集成定时器构成的多谐振荡器计算得到。

两个可预置四位二进制计数器74LS163构成秒计数器电路，两个七段译码驱动器74LS248以及电灯构成数码显示器电路，其中下方的七段译码驱动器74LS248可以不用，可以直接接四接口电灯。

电路中其他元件（开关以及四2输入与非门74LS00、双4输入与非门74LS20）构成控制电路。

其中开关1起清零作用，开关2起暂停作用。

七、实验体会

这是本学期最后一次实验，也是考试实验，该实验考察了本学期学习的各个元件特别是计数器的实验是本学期实验的一大重点，同时自行设计电路也让我们学会将所学知识结合运用，合理协调配合得到我们想要方案。操作实验中我们进行的并不是非常顺利，主要因为之前没有进行充分的复习准备，同时操作时应注意各个接口的接触，以及七段译码驱动器74LS248运行需接上拉电阻等细节问题。

33

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